Formal Specification and Research

Formal Specification and Research


Formal Specification has long history in the academic field. It is interesting that large amount is research is done in academics regarding formal specification

UML/SDL are actually implementation of the Formal specification in the Graphical Domain.

If you are interested in the research aspect of the formal specification and systems engineering please follow this link.

Please remember these are research tools at the present moment.
The ideas and projects will give you future directions to come in Software Engineering and Systems Engineering discipline.

Formal Specification can be used for Hardware Design for such language as VHD/Verilog/SystemsC and also in software design such as C++/C#

Formal Specification has not entered the Formal HYPE CYCLE ( still considered sissy-IE. difficult to understand) as they say it in academics.

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Last modified on Friday, 15 April 2016 20:49

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